Power Minimisation Techniques for Testing Low Power VLSI Circuits (PhD Dissertation)

Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. The first part of this dissertation addresses power minimisation techniques in scan sequential circuits at the logic level of abstraction. A new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits. Since the proposed test application strategy depends only on controlling primary input change time, power is minimised with no penalty in test area, performance, test efficiency, test application time or volume of test data. Furthermore, it is shown that partial scan does not provide only the commonly known benefits such as less test area overhead and test application time, but also less power dissipation during test application when compared to full scan. To achieve power savings in large scan sequential circuits a new test set independent multiple scan chain-based technique which employs a new design for test (DFT) architecture and a novel test application strategy, is presented. The technique has been validated using benchmark examples, and it has been shown that power is minimised with low computational time, low overhead in test area and volume of test data, and with no penalty in test application time, test efficiency, or performance. The second part of this dissertation addresses power minimisation techniques for testing low power VLSI circuits using built-in self-test (BIST) at RTL. First, it is important to overcome the shortcomings associated with traditional BIST methodologies. It is shown how a new BIST methodology for RTL data paths using a novel concept called test compatibility classes (TCC) overcomes high test application time, BIST area overhead, performance degradation, volume of test data, fault-escape probability, and complexity of the testable design space exploration. Second, power minimisation in BIST RTL data paths is achieved by analysing the effect of test synthesis and test scheduling on power dissipation during test application and by employing new power conscious test synthesis and test scheduling algorithms. Third, the new BIST methodology has been validated using benchmark examples. Further, it is shown that when the proposed power conscious test synthesis and test scheduling is combined with novel test compatibility classes simultaneous reduction in test application time and power dissipation is achieved with low overhead in computational time

Low power test compatibility classes: exploiting regularity for simultaneous reduction in test application time and power dissipation

Traditional DFT methodologies increase useless power dissipation during testing and are not suitable for testing low power VLSI circuits leading to lower reliability and manufacturing yield. Traditional test scheduling approaches based on fixed test resource allocation decrease power dissipation at the expense of higher test application time. On the one hand it was shown that power conscious test synthesis and scheduling eliminate useless power dissipation. On the other hand by exploiting regularity in BIST RTL data paths using test compatibility classes an improvement in test application time, BIST area overhead, performance degradation, volume of test data, and fault escape probability is achieved. This paper shows that when combining power conscious test synthesis and scheduling with the test compatibility classes into low power test compatibility classes, simultaneous reduction in test application time and power dissipation is obtained

Power minimisation techniques for testing low power VLSI circuits

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Addressing Useless Test Data in Core-Based System-on-a-Chip Test

This paper analyzes the test memory requirements for core-based systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chains designs. Although useless test data does not represent any relevant test information, it is often unavoidable, and it leads to the trade-off between the test bus width and the volume of test data in multiple scan chains-based cores. Ultimately this trade-off influences the test access mechanism design algorithms leading to solutions that have either short test time or low volume of test data. Therefore, in this paper, a novel test methodology is proposed, which by dividing the wrapper scan chains into two or more partitions, and by exploiting automated test equipment memory management features reduces the useless memory. Extensive experimental results using ISCAS89 and ITC02 benchmark circuits are provided to analyze the implications of the number of wrapper scan chains in the partition, and the number of partitions on the proposed methodology

Tackling Test Trade-offs for BIST RTL Data Paths: BIST Area Overhead, Test Application Time and Power Dissipation

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation. Using a complex validation flow and experimental data for over 30,000 testable data paths, it is shown how test application time decreases asymptotically when increasing power constraints. Further, it is experimentally demonstrated why power conscious test synthesis and test scheduling algorithms are required due to large variations in useless power dissipation as test application time decreases. Finally, while previous research has outlined that test application time decreases as BIST area overhead increases, this paper shows that in order to reach high quality solutions in terms of test application time and BIST area overhead under given power constraints, a three dimensional design space needs to be explored